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BQ2081
SLUS502 - SEPTEMBER 2001
SBS COMPLIANT GAS GAUGE IC FOR USE WITH THE bq29311
FEATURES D Provides Accurate Measurement of Available D D
Charge in Li-Ion and Li-Polymer Batteries Supports the Smart Battery Specification (SBS) V1.1 Works With the TI bq29311 Protection IC to Provide Complete Pack Electronics for 10.8-V or 14.4-V Battery Packs with Few External Components Based on a Powerful Low-Power RISC CPU Core With High-Performance Peripherals Integrated FLASH Memory Eliminates the Need for External Configuration EEPROM Measures Charge Flow Using a High Resolution 15-Bit Integrating Converter - Better Than 3-nVh of Resolution - Self-Calibrating - Offset Error Less Than 1-V Uses 15-Bit Delta Sigma Converter for Accurate Voltage, Temperature, and Current Measurements Programmable Cell Modeling for Maximum Battery Fuel Gauge Accuracy Drives 4- or 5-Segment LED Display for Remaining Capacity Indication 38-pin TSSOP (DBT) The BQ2081 uses an integrating converter with continuous sampling for the measurement of battery charge and discharge currents. Optimized for coloumb counting in portable applications, the self-calibrating integrating converter has a resolution better than 3-nVh and an offset measurement error of less than 1-V (typical). For voltage, temperature, and current reporting, the BQ2081 uses a 15-bit A-to-D converter. In conjunction with the bq29311, the onboard ADC also monitors individual cell voltages in a battery pack and allows the BQ2081 to generate the control signals necessary to implement the required safety protection for Li-Ion and Li-Polymer battery chemistries. The BQ2081 supports the smart battery data (SBData) commands and charge control functions. It communicates data using the System Management Bus (SMBus) 2-wire protocol or the 1-wire HDQ16 protocol. The data available includes the battery's remaining capacity, temperature, voltage, current, and remaining run-time predictions. The BQ2081 provides LED drivers and a push button input to depict remaining battery capacity from full to empty in 20% or 25% increments with a 4 or 5 segment display. The BQ2081 contains 512 bytes of internal FLASH EPROM, whith store configuration information. The information includes nominal capacity and voltage, self-discharge rate, rate compensation factors, and other programmable cell-modeling factors used to accurately adjust remaining capacity for use-conditions based on time, rate, and temperature. The BQ2081 also automatically calibrates or learns the true battery capacity in the course of a discharge cycle from programmable near full to near empty levels. The bq29311 protection IC provides power to the BQ2081 from a 3 or 4 series Li-Ion cell stack, eliminating the need for an external regulator circuit.
D D
D D D D
DESCRIPTION
The BQ2081 SBS Compliant gas gauge IC for battery pack or in-system installation maintains an accurate record of available charge in Li-Ion or Li-Polymer batteries. The BQ2081 monitors capacity and other critical parameters of the battery pack and reports the information to the system host controller over a serial communication bus. It is designed to work with the bq29311 protection IC to maximize functionality and safety and minimize component count and cost in smart battery circuits.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright 2001, Texas Instruments Incorporated
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PRODUCT PREVIEW
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BQ2081
SLUS502 - SEPTEMBER 2001
Terminal Functions
TERMINAL NAME CLKOUT DISP FILT HDQ16 INT LED1 LED2 LED3 LED4 LED5 MRST N/C No. 35 25 32 14 17 20 21 22 23 24 26 4, 5, 7, 12, 13, 18, 36, 37 3 9 6 10 15 16 28 27 2 31 8 1 30 11, 19, 38 29 34 33 I/O I I I I/O I O O O O O I - I I O I/O I/O I/O I I I I I I I I I I O Master reset input that forces the device into reset when held high No connection Analog input for auto ADC offset compensation. Register backup that provides backup potential to the BQ2081 registers during periods of low operating voltage. RBI accepts a storage capacitor or a battery input. Communication clock to the bq29311 Data transfer to and from bq29311 SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the BQ2081 SMBus data open-drain bidirectional pin used to transfer address and data to and from the BQ2081 Connections for a small-value sense resistor to monitor the battery charge- and discharge-current y g g flow Thermistor voltage input connection to monitor temperature Positive supply for analog circuitry Positive supply for digital circuitry and I/O pins Single cell voltage input from the bq29311 Negative supply for analog circuitry Negative supply for digital circuitry Negative supply for output circuitry 32.768kHz crystal oscillator input pin 32.768kHz crystal oscillator output pin 32.768-kHz output to the bq29311 Display control for the LED drivers LED1 through LED5 Serial memory clock for data transfer between the bq2063 and the external nonvolatile configuration memory Serial communication open-drain bidirectional communications port Safety interrupt from the BQ2081 LED display segments that each may drive an external LED yg y DESCRIPTION
PRODUCT PREVIEW
OC RBI SCLK SDATA SMBC SMBD SR1 SR2 TS VDDA VDDD VIN VSSA VSSD VSSP XCK1 XCK2
AVAILABLE OPTIONS PART NUMBER BQ20811DBT PACKAGE (38-PIN TSSOP) Standard device
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BQ2081
SLUS502 - SEPTEMBER 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, VDD relative to VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Open-drain I/O pins, V(IOD) relative to VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Input voltage range to all other pins, VI relative to VSS (see Note 1) . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: 1: VSS refers to the common node of V(SSA), V(SSD), and VSS.
electrical characteristics for VDD = 3.0 V to 3.6 V, TA = -20C to 70C (unless otherwise noted)
PARAMETER VDD IDD I(SLP) VI(OLS) V(IL) VIH VOL V(ILS) V(IHS) V(AI) I(RB) V(RBI) Z(AI1) Z(AI2) Supply voltage Operating current Low-power storage mode current Output voltage low: (LED1-LED5) Input voltage low DISP Input voltage high DISP Output voltage low SMBC, SMBD, HDQ16, SDATA, SCLK Input voltage low SMBC, SMBD, HDQ16, SDATA, SCLK Input voltage high SMBC, SMBD, HDQ16, SDATA, SCLK Input voltage range VIN, TS, OC RBI data-retention input current RBI data-retention voltage Input impedance SR1, SR2 Input impedance VIN, TS, OC 0 V-1.0 V 0 V-1.0 V V(RBI) > 3 V, VCC < 2.5 V 1.3 10 8 IOL = 0.5 mA -0.3 1.7 VSS - 0.3 10 I(OLS) = 10 mA -0.3 2 TEST CONDITIONS MIN 3.0 TYP 3.3 200 1 0.4 0.8 VCC + 0.3 0.4 0.8 6 1.0 50 MAX 3.6 UNIT V A A V V V V V V nA V M M
integrating ADC characteristics, VDD = 3.0 V to 3.6 V, TA= -20C to 70C (unless otherwise noted)
PARAMETER V(SR) V(SROS) INL TEST CONDITIONS MIN -0.3 1 0.003% 0.009% TYP MAX 1.0 UNIT V V Input voltage range, V(SR2) and VSR = V(SR2) - V(SR1) V(SR1) Input offset Integral nonlinearity error
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PRODUCT PREVIEW
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BQ2081
SLUS502 - SEPTEMBER 2001
SMBus timing specifications, TA = -20C to 70C, 3.0 V < VDD < 3.6 V (unless other noted)
PARAMETER FSMB FMAS TBUF THD:STA TSU:STA TSU:STO THD:DAT TSU:DAT TTIMEOUT TLOW THIGH TLOW:SEXT TLOW:MEXT SMBus operating frequency SMBus master clock frequency Bus free time between start and stop Hold time after (repeated) start Repeated start setup time Stop setup time Receive mode Data hold time Data setup time Error signal/detect Clock low period Clock high period Cumulative clock low slave extend time Cumulative clock low master extend time Clock/data fall time Clock/data rise time See Note 2 See Note 3 See Note 4 See Note 5 See Note 6 See Note 1 Transmit mode TEST CONDITIONS Slave mode, SMBC 50% duty cycle Master mode, no clock low slave extend 4.7 4.0 4.7 4.0 0 300 250 25 4.7 4.0 50 25 10 300 1000 35 MIN 10 51.2 TYP MAX 100 UNIT kHz kHz s s s s s s s ms s s ms ms ns ns
PRODUCT PREVIEW
TF TR
NOTES: 1. The BQ2081 times out when any clock low exceeds TTIMEOUT 2. THIGH Max. is minimum bus idle time. SMBC = SMBD = 1 for t > 50 s causes reset of any transaction involving BQ2081 that is in progress. 3. TLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. 4. TLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. 5. Rise time TR = (VILMAX - 0.15 V) to (VIHMIN + 0.15 V). 6. Fall time TF = 0.9 VDD to (VILMAX - 0.15 V).
HDQ timing characteristics, TA = -20C to 70C, 3.0 V < VDD < 3.6 V (unless otherwise noted)
PARAMETER tc(CYCH) tc(CYCB) th(STRH) th(STRB) tsu(DSU) tsu(DSUB) th(DH) t(DV) tsu(SSU) tsu(SSUB) t(RSPS) t(B) t(BR) Cycle time, host to BQ2081 (write) Cycle time, BQ2081 to host (read) Start hold time, host to BQ2081 (write) Start hold time, host to BQ2081 (read) Data setup time Data setup time Data hold time Data valid time Stop setup time Stop setup time Response time, BQ2081 to host Break time Break recovery time 190 190 40 100 80 145 145 320 TEST CONDITIONS MIN 190 190 5 32 50 50 205 250 TYP MAX UNIT s s ns s s s s s s s s s s
Figures 6-9 are timing diagrams for the BQ2081 .
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BQ2081
SLUS502 - SEPTEMBER 2001
TSSOP PACKAGE (TOP VIEW)
17 18 19
22 21 20
SMBus timing diagrams
SCLK TLOW TR TF THD:STA
THD:STA THD:DAT SDATA TBUF P S Start
THIGH
TSU:STA TSU:DAT
TSU:STO
S Stop TLOW:SEXT SCLKACK SCLKACK TLOW:MEXT TLOW:MEXT
P
TLOW:MEXT
SCLK
SDATA
SCLKACK is the acknowledge-related clock pulse generated by the master.
Figure 1. SMBus Timing Diagram
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PRODUCT PREVIEW
VIN TS OC N/C N/C SCLK N/C VDDD RBI SDATA VSSD N/C N/C HDQ16 SMBC SMBD INT N/C VSSD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
VSSD N/C N/C CLKOUT XCK1 XCK2 FILT VDDA VSSA VSSP SR2 SR1 MRST DISP LED5 LED4 LED3 LED2 LED1
BQ2081
SLUS502 - SEPTEMBER 2001
HDQ timing diagrams
t(BR) t(B)
Figure 2. HDQ Break Timing
Write "1" Write "0" th(STRH) tsu(DSU) th(DH)
PRODUCT PREVIEW
tsu(SSU) tc(CYCH)
Figure 3. HDQ Host to BQ2081
Read "1" Read "0" th(STRB) tsu(DSUB) t(DV) tsu(SSUB) tc(CYCB)
Figure 4. HDQ BQ2081 to Host
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typical application
8 VDDD 1 VIN HDQ16 FILT OC 3 TS 2 SMBC SMBD NC NC LED5 LED4 LED3 LED2 36 18 20 21 22 23 24 LED1 DISP 25 16 15 32 XCK1 34 XCK2 14 26 33
31 VDDA
23 DSG 21 CHG VPACK VREG TOUT LEDOUT SCLK SDATA XALERT CLKIN 12 SR2 9 VCELL GND GND 13 11 16 17 15 14 20 18 19 24 1 VCC VBAT CNTL VC1 VC2 VC3 VC4 VC5 SR1 8 2 10 3 4 5 6 7
APPLICATION INFORMATION
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22 PCHG VSSD VSSD VSSD VSSA 11 38 30 19
MRST 9 RBI 12 DFC 10 SDATA 6 SCLK 7 NC 17 INT 35 CLKOUT 28 SR1 27 SR2 4 NC 13 CFC 5 NC 37 NC 29 VSSP
D6
D5
D4
D3
SLUS502 - SEPTEMBER 2001
BQ2081
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PRODUCT PREVIEW
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Copyright 2001, Texas Instruments Incorporated

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